For reducing electromigration effect in an integrated circuit

ABSTRACT

An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.

FIELD OF THE INVENTION

This invention relates to improvements for reducing electromigrationeffect in an integrated circuit and more particularly describes a newmethod and apparatus for integrated circuit layout to reduceelectromigration failures.

BACKGROUND OF THE INVENTION

In an integrated circuit, many different electronic devices orcomponents such as transistors or capacitances are formed in or on aspecific substrate, which generally has a planar configuration. Thelayer may be a metal dielectric or any other type of materialappropriate to the circuit design. The electrical connections betweenthe electronic devices located on the substrate or on a surface of adielectric layer occurs through a network of metal interconnects orinterconnections. Generally, complex integrated circuits are formed withdifferent metal layers or levels. The network of interconnects mayinclude intra-level connections also called metal lines which makeconnections in the same layer and inter-level connections called vias,which, are metal links which connect consecutive metals layers.

Metal lines and vias represent metallization layers also calledinterconnections or interconnects of an integrated circuit.Interconnections may be made of Copper, Aluminium, or any otherconducting material. Most recent integrated circuits use Copper as theinterconnection material as Copper has a better electrical conductivityand a better electromigration resistance than Aluminium. Integratedcircuit interconnects generally comprise a diffusion barrier liner inorder to separate vias of metal material from layers of dielectricmaterial located above and below the vias. The barrier liner is made ofa specific material impermeable to Copper or Aluminium for example, inorder to prevent the diffusion of metal material into dielectricmaterial.

A phenomenon called electromigration is a well-know problem inelectronic integrated circuits. Electromigration occurs when a currentflows in an integrated circuit. Electromigration relates to displacementof atoms in an interconnect such as metal lines or vias. The movement ofatoms produces a void of atoms of Copper for example at one part of theinterconnect and accumulation of Copper at another part of theinterconnect. This movement of atoms can produce weakness in theinterconnect and may ultimately lead to failure: either due toopen-circuits caused by voids, or by short-circuits caused by Copperaccumulation and cracking of the dielectric material.

When electromigration occurs in an electronic circuit, which comprises abarrier liner, two effects are visible. Firstly in the interconnect,movement of atoms leads to voids of atoms above or below the barrierliner, depending on current flow and secondly movement of atoms alsoleads to accumulation of atoms below or above the barrier liner. Thismovement of atoms in the interconnect may produce failures in theelectronic circuit as above. In short, barrier liners at the via bottomstop the movements of the metal atoms. Thus, by far the mostelectromigration failure sites are located at the barrier liner.

In order to avoid the voids and accumulations of atoms, U.S. Pat. No.6,380,075 discloses a solution using a specific process called the“punch through barrier deposition process” where the barrier liner isonly made on the sidewalls of vias. The bottom of the via is free ofbarrier liner. Thus, when a current flows in the electronic circuit,atoms of Copper are no longer stopped and accumulated at the barrierliner. Therefore, electromigration is reduced. However the problem ofaccumulation of atoms at the other side of the interconnect stillremains unresolved and leads to further electromigration degradationproblems.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method and apparatuswhich overcomes at least some of the problems associated with the priorart.

According to one aspect of the invention there is provided a method andan apparatus for integrated circuit layout as described in theaccompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made, by way of example, to the accompanyingdrawings, in which:

FIG. 1 is a circuit layer diagram of a first electronic integratedcircuit, of the prior art.

FIG. 2 a is a circuit layer diagram of an electronic integrated circuit,in accordance with one embodiment of the invention, given by way ofexample,

FIG. 2 b is a circuit layer diagram of an electronic integrated circuit,in accordance with one embodiment of the invention, given by way ofexample,

FIG. 3 is a circuit layer diagram of an electronic integrated circuit,in accordance with one embodiment of the invention, given by way ofexample,

FIG. 4 is a circuit layer diagram of an electronic integrated circuit,in accordance with one embodiment of the invention, given by way ofexample and

FIG. 5 is a flowchart of the method steps, in accordance with oneembodiment of the invention, given by way of example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a layer structure 100 of an electronic integrated circuitas known in the prior art. An electronic component 110 such as atransistor or a capacitance for example is located on the bottom of thestructure. Another similar electronic component 112 or a bondpad islocated at the top of the structure.

Layers 114 and 116 separate both components and are defined asinter-level dielectric layers. Inter-level dielectric layers 114 and 116are made of dielectric material. Layers 114 and 116 compriseinterconnects defined as metal lines 118,120 and vias 122,124. Bothmetal lines and vias are made of Copper or Aluminium for example. Abarrier line 126, 128 forms a separation between interconnects 118, 120,122, 124 and inter-level dielectric layer 114 and 116. The barrier liner126, 128 is not provided at the bottom of both vias 122, 124. Thedeposition of such a barrier liner occurs through a well-known processcalled “punch through deposition barrier process”.

FIG. 2 a describes a modified structure as defined in the presentinvention. Metal line 118 comprises specific zones 130 and 132 on bothextremities of metal line 118. The zones 130 and 132 belong to theoriginal metal line and are called sink zones or receptor zones.Differing from prior art and original metal line, both zones can be madeof a specific material called receptor material such as a porousmaterial different from Copper or Aluminium material. The material canbe for example a porous low k such as SiCOH. The function of zones 130and 132 called receptor zones is to absorb atoms of Copper duringelectromigration effect when a current flows in the electronic circuitas will be described later in further details. Ideally, the material ofthe interconnect is already a porous dielectric material or low kmaterial, thus no additional process steps are required. If theintegration uses a non-porous dielectric the sink zones are formed by aporous low k material commonly used in industry. The sink zones must bechosen to be large enough to allow all the Copper, which migrates duringthe expected life of the device, to accumulate.

As shown in FIG. 2 b, an alternative modification of the original metalline 118 is to put a relatively malleable material inside zones 130 and132 or all around the metal line 118. In this way, the malleablematerial can absorb atoms of Copper by extending the length of zones 130and 132. Differing from the previous solution, as the zones areextendible with the malleable material, the zones do not show anyaccumulation of Copper atoms. Thus, zones 130 and 132 do not create anydegradation in the electronic circuit.

Another alternative modification of the original metal line 118 is tonot use any dielectric material at all, and instead use a so calledairgap. In the case of airgaps, Copper atoms are free to accumulate. Thedistance between lines must be designed to be sufficiently large toallow accumulation without causing shorting.

FIG. 3 shows a modified structure as defined in the present invention.Metal line 120 comprises a specific zone 134. This zone 134 called thesource zone or donor zone may or may not already belong to the metalline 120. This zone 134 is made of a donor material. This zone may be abondpad made of Copper already used in the electronic circuit 100 inorder to connect the circuit with an outside device. This zone 134 canalso be an additional zone made of Copper. The function of the specificzone 134 is to release atoms of Copper during electromigration effect aswill be described later as a result the specific zone 134 may bereferred as a donor zone.

The process in accordance with the present invention includes a numberof steps.

The first step is to detect the movement of atoms of Copper ininterconnects during electromigration phenomenon. A specific simulationtool, for example a tool having a three dimensional Poisson solvermodule can carry out the detection. The aim of the detection is tolocate weakness zones around areas of high current density where atomsof Copper accumulate and/or are depleted. The zones are generallylocated as described in FIG. 4. As previously mentioned zones 130 and132 refer to receptor zones where atoms of Copper generally accumulateduring electromigration effect. Therefore, the process allows creationof a sink in order to receive all the Copper atoms coming into this zonewhen electromigration effect occurs. As previously mentioned donor zone134 refers to a zone where atoms are depleted. Therefore, the processallows creation of a source in order to donate all Copper atoms from thesource without damaging the existing Copper material of the integratedcircuit. After identifying and localizing these zones, the circuitdesign is altered to include space for the sink zones which are thenformed during the building of the device. The simulation tool alsoprovides information on how to fill zone 134 with Copper whilst thedevice is built. If donor zone 134 already refers to a zone already madeof Copper material such as a bond pad for example, the simulation tooldoes not carry out any filling up.

The behaviour of an electronic circuit, as defined in the presentinvention, will now be described when a current flows therein.

When a current is applied to the electronic circuit 100, atoms of Copperin the interconnects are free to move from one interconnect to anotherin another layer as there is no barrier liner at the bottom of the vias.Atoms of Copper move in the same direction as the flow of electrons i.e.in an opposite direction to the current. Therefore as indicated on FIG.4, atoms of Copper migrate from metal line 120 to metal line 118. Morespecifically, atoms of Copper move from zone 134 to zones 130 and 132.As zone 134 is well provided with atoms of Copper through existing bondpads or through additional Copper material, zone 134 keeps a homogeneoussurface. This means that no weakness, failures or cracks appear in zone134 during electromigration process. Similarly, as zones 130 and 132 areprovided with specific porous material or malleable material, thisspecific material can absorb all atoms of Copper coming frominterconnect 118 or 120. Therefore, no accumulation occurs in zones 118and 120. Therefore, no degradation occurs in the electronic circuitbecause of void formation along the interconnect or accumulation on theinterconnect, at these specific zones 118 and 120.

Indeed, the present invention refers to electromigration phenomenon inan integrated circuit using a punch through barrier deposition processto avoid having a barrier liner at the bottom of vias. The presentinvention allows compensating movement of atoms of Copper during theelectromigration phenomenon, using the barrier-free via bottom process.The modification of specific zones in the interconnects allows thecreation of a compensation process in order to avoid failures in theinterconnect. Specific zones are provided with corresponding specificmaterial in order to achieve two different functions: sink function andsource function. The source zone 134 allows a release of atoms of Copperwithout damaging the interconnect. The sink zones 130, 132 allowreception of atoms of Copper without damaging the interconnect.Therefore, electrical conductivity of electronic circuit is maintainedwhen electromigration effect occurs.

Examples of combinations, metals, different circuits, different zones,(all or some) look at all the variations.

It will be appreciated that the examples described above are just thatand many other alternatives may exist, which fall within the scope ofthe present invention.

1. An integrated circuit comprising: one or more dielectric layers, eachdielectric layer being provided with one or more interconnects, whereinthe interconnect comprises metallic atoms moving from a first region ofthe interconnect to a second region of the interconnect when a currentflows, wherein the interconnect comprises: a donor zone in the firstregion of the interconnect wherein the first region comprises an atomdonor material for providing metallic atoms in order to compensate formovement of atoms from the first region, characterised in that theinterconnect comprises: a receptor zone at the second region of theinterconnect wherein the second region comprises a porous material forreceiving metallic atoms in order to compensate for movement of atoms tothe second region.
 2. An integrated circuit as claimed in claim 1,wherein the atom donor material is selected from a list which includesCopper and Aluminium.
 3. An integrated circuit as claimed in claim 1,wherein the first region is provided by a metal line of the integratedcircuit.
 4. An integrated circuit as claimed in claim 1, wherein thefirst region is provided by a bondpad of the integrated circuit.
 5. Anintegrated circuit as claimed in claim 1, wherein the porous material isa porous low k material.
 6. An integrated circuit as claimed in claim 1,wherein the second region comprises a malleable material.
 7. A method ofmanufacturing an integrated circuit having reduced electromigrationeffect, wherein the integrated circuit comprises one or more dielectriclayers, each dielectric layer being provided with one or moreinterconnects, wherein the interconnect comprises metallic atoms movingfrom a first region of the interconnect to a second region of theinterconnect when a current flows, characterized in that said methodcomprises: locating a first and a second region in the one or moreinterconnects; filling the first region with a first type of material tocreate a donor zone; filling the second region with a second type ofmaterial to create a receptor zone; substantially compensating movementof atoms from the first region to the second region to reduceelectromigration effect further comprising providing atoms from thedonor material in the first region and receiving atoms from the receptormaterial in the second region and wherein the step of receiving atomsfrom the receptor material comprises a step of selecting a receptormaterial which includes porous low k materials.
 8. A method as claimedin claim 7, wherein the step of providing atoms from the donor material,comprises a step of selecting the donor material from a list whichincludes Copper and Aluminium.
 9. A method as claimed in claim 7,wherein the step of filling the first region comprises providing amaterial of Copper.
 10. A method as claimed in claim 7, wherein the stepof filling the second region comprises filling the second region with aporous material.
 11. An integrated circuit as claimed in claim 2,wherein the first region is provided by a metal line of the integratedcircuit.
 12. An integrated circuit as claimed in claim 2, wherein thefirst region is provided by a bondpad of the integrated circuit.
 13. Anintegrated circuit as claimed in claim 3, wherein the first region isprovided by a bondpad of the integrated circuit.
 14. An integratedcircuit as claimed in claim 2, wherein the porous material is a porouslow k material.
 15. An integrated circuit as claimed in claim 3, whereinthe porous material is a porous low k material.
 16. An integratedcircuit as claimed in claim 4, wherein the porous material is a porouslow k material.
 17. An integrated circuit as claimed in claim 2, whereinthe second region comprises a malleable material.
 18. An integratedcircuit as claimed in claim 3, wherein the second region comprises amalleable material.
 19. An integrated circuit as claimed in claim 4,wherein the second region comprises a malleable material.
 20. Anintegrated circuit as claimed in claim 5, wherein the second regioncomprises a malleable material.